The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (“I/O”) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions. The I/O devices are operative to interact with a user through a graphical user interface (“GUI”) (such as provided by Microsoft Windows™ or IBM OS/2™), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor's power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, there is a practical maximum to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (“processor throughput”). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a “pipeline”). Instructions are processed in an “assembly line” fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
“Superpipelining” extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is “superscalar” processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (“degree of scalability”). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (“bubbles” or “stalls”) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor's architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized. Statistically, certain instructions are executed more frequently than others are. If the design of a processor is optimized to rapidly process the instructions that occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
Many processors are called upon to accommodate numbers in two different formats: integer and floating point. Integers are whole numbers that contain no fractional parts and that may be represented in both positive and negative senses usually up to a limit of several multiples of the word length (extended precision) in the processor. Floating point numbers equate to scientific notation and may be used to represent any number. Bit positions in the floating point word accommodate sign, exponent and mantissa for the number. IEEE Floating Point Standards allow 1 bit for sign, 8 to 15 bits for exponent and 23 to 64 bits for mantissa respectively for formats ranging from single precision to double extended precision. Floating point units are specifically designed to process floating point numbers in order to gain throughput efficiencies over using a general purpose processor.
Current floating point units (FPUs), although much faster than general purpose processors, are not optimized all that much for throughput speed. There are often many exceptions in the processing of floating point numbers and many FPUs use microcode or software traps to accommodate these conditions which causes processing speed to decrease. Additionally, some recirculation of instructions or data may be necessary in some FPUs. That is, the contents of the FPU may have to make several passes through to accomplish its goal.
Floating point numbers are often represented in their denormal state which means that the decimal/binary point may be located anywhere in the number. The floating point number must usually be normalized in order to be processed in an FPU. Normalized representation requires that each floating point number start with a “1” just to the left of the “point” requiring a denormal number to be shifted and its exponent adjusted before further processing can occur. Increasing floating point processing demands created by explosive user interest in areas requiring more graphics, video and sound synthesis applications is driving the need for faster and better approaches to process floating point numbers at ever-increasing throughput speeds.
Therefore, what is needed in the art is a way to further increase floating point instruction processing predictability and speed without adding undue hardware complexity.